1. Field of the Invention
The present invention relates to a device and a method for demodulating data by means of DQPSK (Differential Quadrature Phase Shift Keying) system.
2. Description of the Background Art
With the recent arrival of the IT (Information Technology) revolution represented by the Internet, the concept of home network is being turned into reality. As an example of the home network, a standard called ECHONET is now receiving attention.
ECHONET implements a network structured by utilizing home electric lines. Then, no investment is required in a new infrastructure, which is one of characteristics of ECHONET. Data transmission by this ECHONET is accomplished by employing a DQPSK modulation-demodulation system.
FIG. 1 is a block diagram schematically showing a structure of a conventional demodulator employing the DQPSK system. The conventional demodulator of the DQPSK system includes an FFT calculation unit 101 performing a fast Fourier transform (FFT) on a modulated waveform transmitted thereto to separate frequency components from the modulated waveform and thus outputting information about coordinates, on an xy plane, of a frequency to be processed, an angle calculation unit 102 performing a calculation on the xy coordinate information supplied from FFT calculation unit 101 to determine an angle value, a first register 103 holding a current angle value supplied from angle calculation unit 102, a second register 104 holding a preceding angle value supplied from angle calculation unit 102, a subtractor 105 subtracting the preceding angle value held in the second register 104 from the current angle value held in the first register 103, a third register 106 holding the difference between the angle values (angular difference) supplied from subtractor 105, an adder 107a adding angle xe2x80x9cxe2x88x927xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107b adding angle xe2x80x9cxe2x88x925xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107c adding angle xe2x80x9cxe2x88x923xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107d adding angle xe2x80x9cxe2x88x921xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107e adding angle xe2x80x9c+1xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107f adding angle xe2x80x9c+3xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107g adding angle xe2x80x9c+5xcfx80/4xe2x80x9d to the angular difference held in the third register 106, an adder 107h adding angle xe2x80x9c+7xcfx80/4xe2x80x9d to the angular difference held in the third register 106, a demapper 108 converting the angular difference into a 2-bit code according to the resultant sums supplied from adders 107a to 107h, and a fourth register 109 holding the code resultant from demapping by demapper 108.
FFT calculation unit 101 separates an analogue waveform transmitted through an electric line (not shown) into frequency components to output an x coordinate value and a y coordinate value, on the xy plane, of a frequency component as a sample to be processed.
Angle calculation unit 102 performs a calculation by means of approximate expressions on the x and y coordinate values supplied from FFT calculation unit 101 to determine a vector length and an angle value of the frequency corresponding to a current sample. The angle value has a range of xe2x80x9c0-2xcfx80xe2x80x9d.
Synchronously with output of the angle value from angle calculation unit 102, the first register 103 holds that angle value. At the same timing as that of holding the angle value by the first register 103, the second register 104 holds an angle value supplied from the first register 103. Accordingly, when the first register 103 holds an angle value of a next sample, the second register 104 holds an angle value of a preceding sample.
Subtractor 105 subtracts the angle value of the preceding sample held in the second register 104 from the angle value of the current sample held in the first register 103 to output the difference between the angle values (angular difference). The third register 106 holds and then outputs the angular difference supplied from subtractor 105.
Angle calculation unit 102 calculates, from the x and y coordinate values, an angle value with the range of xe2x80x9c0-2xcfx80xe2x80x9d as described above. Accordingly, respective angle values held in the first and second registers 103 and 104 also have the range of xe2x80x9c0-2xcfx80xe2x80x9d. The angular difference supplied from subtractor 105 thus has a range of xe2x80x9cxe2x88x922xcfx80xe2x80x942xcfx80xe2x80x9d. Then, in order to demap the angular difference held in the third register 106, it is necessary to determine which of nine values, i.e., xe2x80x9cxe2x88x922xcfx80, xe2x88x923xcfx80/2, xe2x88x92xcfx80, xe2x88x92xcfx80/2, 0, xcfx80/2, xcfx80, 3xcfx80/2, 2xcfx80xe2x80x9d is the angular difference.
However, in the actual demodulator, the angular difference calculated by subtractor 105 has certain variation and extent because of considerable influences of noise and distortion and the fact that the calculation is performed by means of approximate expressions. Then in consideration of the variation and extent, the determination is made as detailed below.
The determination above requires another determination as to in which region the angular difference is included. Then, a value corresponding to the boundary of each region and the angular difference undergo addition and subtraction and a sign bit of a resultant value is examined to detect a region in which the angular difference is included. Adders 107a to 107h each calculate a sum of the angular difference and the value corresponding to the boundary of each region.
For example, in order to determine whether the angular difference is greater than xe2x80x9c+7xcfx80/4xe2x80x9d, adder 107a adds xe2x80x9cxe2x88x927xcfx80/4xe2x80x9d to the angular difference and outputs the most significant bit of the resultant sum as a sign bit. If the angular difference is greater than xe2x80x9c+7xcfx80/4xe2x80x9d, the resultant sum is a positive value and the sign bit supplied from adder 107a is xe2x80x9c0xe2x80x9d. On the contrary, if the angular difference is smaller than xe2x80x9c+7xcfx80/4xe2x80x9d, the resultant sum is a negative value and the sign bit supplied from adder 107a is xe2x80x9c1xe2x80x9d. Similarly, adders 107b to 107h make determination regarding respective boundary values xe2x80x9cxe2x88x925xcfx80/4xe2x80x9d, xe2x80x9cxe2x88x923xcfx80/4xe2x80x9d, xe2x80x9cxe2x88x921xcfx80/4xe2x80x9d, xe2x80x9c+1xcfx80/4xe2x80x9d, xe2x80x9c+3xcfx80/4xe2x80x9d, xe2x80x9c+5xcfx80/4xe2x80x9d and xe2x80x9c+7xcfx80/4xe2x80x9d.
Demapper 108 inputs respective signs supplied from adders 107a to 107h as 8-bit data and classifies the angular difference from the third register 106 as any of xc2x1nxcfx80/2 (n=0, 1, 2, 3, 4) to accomplish demapping. A relation between signs (inputs) from adders 107a to 107h and a 2-bit code after demapping is shown below. The most significant bit of an input is a sign from adder 107a and the least significant bit thereof is a sign from adder 107h.
The values above are represented according to the syntax of Verilog-HDL (hardware description language). For example, xe2x80x9c8xe2x80x2bxe2x80x9d and xe2x80x9c2xe2x80x2bxe2x80x9d means that subsequent values are represented by 8-bit binary number and 2-bit binary number respectively. xe2x80x9c32xe2x80x2hxe2x80x9d means that subsequent values are represented by 32-bit hexadecimal number.
The fourth register 109 holds the 2-bit code supplied from demapper 108 and outputs it to a circuit (not shown).
The conventional demodulator of the DQPSK system as described above has a problem that adders 107a to 107h are required for determining in which region an angular difference is included which results in increase in the circuit scale of the demodulator.
One object of the present invention is to provide a demodulator and a demodulation method by which the circuit scale can be reduced.
According to one aspect of the present invention, a demodulator includes a first calculation unit separating an analogue waveform into frequency components to calculate xy coordinate values, on an xy plane, of the frequency components, a first angular difference detector detecting an angular variation value according to respective signs of current xy coordinate values supplied from the first calculation unit and respective signs of preceding xy coordinate values, a second calculation unit calculating an angle value of a frequency component according to respective absolute values of xy coordinate values supplied from the first calculation unit, a subtractor subtracting a preceding angle value from a current angle value supplied from the second calculation unit, a second angular difference detector classifying a subtraction result supplied from the subtractor as one of a plurality of angle regions to detect an angular difference value, and a demapper performing demapping according to a sum of the angular variation value supplied from the first angular difference detector and the angular difference value supplied from the second angular difference detector.
The second calculation unit calculates the angle value of the frequency component according to respective absolute values of the xy coordinate values supplied from the first calculation unit. Circuitry for classifying a result of subtraction supplied from the subtractor as one of a plurality of angle regions can thus be reduced and accordingly the circuit scale of the demodulator can be reduced.
According to another aspect of the invention, a demodulation method includes the steps of separating an analogue waveform into frequency components to calculate preceding xy coordinate values, on an xy plane, of a frequency component, calculating current xy coordinate values on the xy plane of the frequency component, detecting an angular variation value according to respective signs of the calculated current xy coordinate values and respective signs of the preceding xy coordinate values, calculating a preceding angle value of the frequency component according to respective absolute values of the preceding xy coordinate values, calculating a current angle value of the frequency component according to respective absolute values of the current xy coordinate values, subtracting the calculated preceding angle value from the calculated current angle value, classifying a result of the subtraction as one of a plurality of angle regions to detect an angular difference value, and performing demapping according to a sum of the detected angular variation value and the detected angular difference value.
The angle value of the frequency component is calculated according to respective absolute values of the xy coordinate values. Circuitry for classifying a result of subtraction supplied from the subtractor as one of a plurality of angle regions can thus be reduced and accordingly the circuit scale of the demodulator can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.